| INDEX |
 PDF[140KB]
|
| Foreword from President |
PDF[76KB]
|
| Message from Program Leader |
PDF[106KB] |
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1. Outline of the Objectives and Research Results of the 21st Center of Excellence "Nanoelectronics for Tarabit Information Processing"
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PDF[402KB]
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2. Members of the 21st Century COE Program
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PDF[115KB]
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| 3. Achievements, Published Papers, Patents, and Awards |
PDF[170KB] |
| 4. Research Results of Each Subject |
PDF[328KB] |
| 4-I. Circuits and Systems |
4-I-1. Three Dimensional Integration Architecture for Tera-bit Information processing
A. Iwata, M. Sasaki, S. Kameda. H. Ando, T. Yoshida, M. Siozaki, and M. Ono |
PDF[590KB] |
4-I-2. Wireless Chip Interconnect Using Resonant Coupling Between Spiral Inductors
M. Sasaki, D. Arizono, and A. Iwata |
PDF[531KB] |
4-I-3. A Brain-type Vision System with Wireless Interconnections
S. Kameda and A. Iwata
|
PDF[296KB] |
4-I-4. Development of Real-time Multi-object Recognition System
H. Ando and A. Iwata |
PDF[434KB] |
4-I-5. A Study on Neural Sensing System
T. Yoshida and A. Iwata |
PDF[476KB] |
4-I-6. CDMA Serial Communication Chips for Highly Flexible Robot Brain
M. Siozaki, A. Iwata, and M. Sasaki |
PDF[257KB] |
4-I-7. Design of a Strategy Learning Model for Robot Brain and LSI Implementation of the Model
M. Ono, M. Sasaki, and A. Iwata |
PDF[231KB] |
4-I-8. Associative-Memory-Based Systems with Recognition and Learning Capability
-Associative Memory for High-Speed Nearest Hamming/Manhattan Distance Search in Large Reference-Pattern Space -
 , T. Koide, Y. Yano, K. Kamimura, and K. M. Rahman |
PDF[958KB] |
4-I-9. Associative-Memory-Based Systems with Recognition and Learning Capability
-Automatic Reference-Pattern Learning and Optimization-
, T. Koide, M. Mizokami, and Y. Shirakawa |
PDF[779KB] |
4-I-10. Image Processing Front End for Associative Memory-Based Systems
-Hardware-Efficient Low-Power Montion-Picture Segmentation by Pipeline Processing of Tiled Images with Cell-Network -
T. Koide, , T. Morimoto, Y. Harada, H. Adachi, and O. Kiriyama |
PDF[974KB] |
4-I-11. Optimized Mixed Digital-Analog Nearest-Match Circuit for Fully-Parallel Associative Memories
K. M. Rahman, K. Kamimura, , and T. Koide |
PDF[321KB] |
4-I-12. Development of Digital-CMOS-Based Real-Time Color -Motion Picture Segmentation Architecture and its LSI Chip Verification
T. Morimoto, T. Koide, and |
PDF[826KB] |
| 4-II. Device Modeling |
4-II-1. TEG Design for HiSIM Model-Parameter Extraction and Parameter Extraction with Single Structures
M. M.-Mattausch, T. Mizoguchi, and Y. Uetsuji |
PDF[282KB] |
4-II-2. Measurement of Thermal Noise for 100nm-MOSFET and Its Modeling
M. M.-Mattausch and S. Hosokawa |
PDF[294KB] |
4-II-3. Inversion Charge Model of SOI-MOSFET for Circuit Simulation and 1/f Noise Analysis
M. M.-Mattausch and N. Sadachika |
PDF[518KB] |
4-II-4. Modeling of Optoelectronic Devices
M. M.-Mattausch, K. Konno, O. Matsushima, K. Hara, and G.Suzuki |
PDF[293KB] |
4-II-5. Modeling of 1/f Noise with HiSIM for 100 nm CMOS Technology
H. Ueno and M. M.-Mattausch |
PDF[1MB] |
4-II-6. Analysis and Modeling of Carrier Transport in Photodiodes
K. Konno and M. M.-Mattausch
| PDF[255KB] |
4-II-7.To Improve HiSIM-SOI for Real Application
M. H. Bhuyan and M. M.-Mattausch |
PDF[183KB] |
| 4-III. Nanodevices and Processing |
4-III-1. Workfunction Tuning for Single-Metal Dual-Gate CMOS
K. Shibahara, K. Sano, and M. Hino |
PDF[2.4MB] |
4-III-2.Fabrication and Evaluation Technique for Ultra-Shallow Junction
K. Shibahara, T. Eto, and E. Takii |
4-III-3. Research and Development of Three-Dimensional MOS Transistors
H. Sunami, K. Okuyama, A. Katakami, K. Kobayashi, and S. Matsumura |
PDF[2.5MB] |
4-III-4. Study in 3-Dimensional new structure MOS Transistor
K. Okuyama, K. Kobayashi, S. Matsumura, and H. Sunam |
PDF[616KB] |
4-III-5. Development of Novel Functional Si-based Devices Using Self-assembled Nanostructures for Multivalued Memory Operation Ultimate Photo-sensing and Molecular Recognition
S. Miyazaki, M. Ikeda, Y. Darma, T. Shibaguchi, S. Higashi, and H. Murakami |
PDF[433KB] |
4-III-6. Control of Si Quantum Dot Nucleation by Remote Plasma Treatment
S. Higashi, K. Makihara, H. Murakami, and S. Miyazaki |
PDF[671KB] |
4-III-7. Low resistive gate electrode/high-k gate dielectrics stacked structure and its electron device application
H. Murakami, Y. Moriwaki, M. Fujitake, D. Azuma, S. Higashi, and S. Miyazaki |
PDF[465KB] |
4-III-8. Control of the Nucleation Density of Si Quantum Dots by Remote Hydrogen Plasma Treatment
K. Makihara, S. Higashi, and S. Miyazaki |
PDF[393KB] |
4-III-9. Investigation on hard breakdown mechanism of high-k gate by conductive-AFM
Pei yanli, S. Higashi, and S. Miyazaki |
PDF[224KB] |
4-III-10. Intra/Inter-Chip Wireless Interconnect System for ULSI (1)
-Si Integrated Antenna-
T. Kikkawa, K. Kimoto, and S. Watanabe |
PDF[549KB] |
4-III-11. Intra/Inter Chip Wireless Interconnect System for ULSI (2)
-A CMOS Ultra Wideband Transmitter-
P. K. Saha, N Sasaki, and T. Kikkawa |
PDF[351KB] |
4-III-12. Intra/Inter-Chip Wireless Interconnect System for ULSI (3)
-A CMOS Ultra Wideband Receiver-
N. Sasaki, P. K. Saha, and T. Kikkawa |
PDF[762KB] |
4-III-13. Intra/Inter Chip Wireless Interconnect System for ULSI (4)
-Low-k/Cu Interconnect -
T. Kikkawa and S. Sakamoto |
PDF[318KB] |
4-III-14. Development of Optically Interconnected LSI
-Integration of Ring Resonator Switches using Electro-Optic Materials-
S. Yokoyama, Y. Tanushi, M. Wake, and K. Wakushima |
PDF[414KB] |
4-III-15. Design and Fabrication of Race-Track Optical Ring Resonator
Y. Tanushi, M. Wake, and S. Yokoyama |
PDF[521KB] |
4-III-16. Etching Properties and Optical Emission Spectroscopy of NH3 Added Pulse-Modulated ICP Plasma
M. Ooka and S. Yokoyama |
PDF[1.0MB] |
4-III-17. Photonic crystal for optoelectronic integrated circuits (OEICs)
-Technology and application of photonic crystal-
A. Nakajima, S. Yokoyama, and M. Wake |
PDF[1.8MB] |
Results
Progress Report(June 2004)