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Profile |
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| Name and Affiliation |
Tetsushi Koide
koide sxsys.hiroshima-u.ac.jp
Associate Professor
Research Center for Nano-devices and Systems
Hiroshima University |
| Education and Professional Background |
| [Education] |
| 1990 |
B.E. degree in physical electronics from Hiroshima University |
| 1992 |
M.E. degree in systems engineering from Hiroshima University |
| 1998 |
D.E. degree in systems engineering from Hiroshima University |
| [Professional] |
| 1992-1999 |
Research Associate in the Faculty of Engineering, Hiroshima University |
| 1999-2001 |
Associate Professor of the Faculty of Engineering, Hiroshima University |
| 1999-2001 |
Associate Professor of the VLSI Design and Education Center (VDEC), University of Tokyo |
| 2001- |
Associate Professor of Research Center for Nanodevices and Systems, Hiroshima University |
| 2001- |
Cooperative Researcher of VLSI Design and Education Center, The University of Tokyo
Research interests include system design and architecture issues for associative memory-based
systems, image processing architecture such as image segmentation, VLSI CAD/DA,
genetic algorithms, and combinatorial optimization. |
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| Academic Societies |
IEEE, Association for Computing Machinery(ACM),
The Institute of Electronics, Information, and Comunication Engineers(IEICE),
Information Processing Society of Japan(IPSJ) |
| Major Research Results |
・Fully-Parallel Associative Memory LSI Architecture (ISSCC'01, JSSC'02)
・High-Speed Pattern Matching LSI Architecuture (VLSI Symp.'02)
・Real-Time Image Segmentation LSI Architecture (SSDM'02, IEICE'04)
・Layout Design Automation Methodologies for System LSI (IEEE Trans. CAD)
・Genetic Algorithm Processor (GECCO'01)
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| Awards |
・1998.2, Young Researcher Award from Inoue Foundation
・2001 LSI IP Design Award, IP Award (Genetic algorithm processor, GAA-II), http://ne.nikkeibp.co.jp/award/
・2002 LSI IP Design Award (A real-time picture-segmentation archictecture for intelligent information processing)
・2002 LSI IP Design Award (A mircoprocessor-core IP for system-LSI research with compatibility to the Super-H instruction set)
・Special Feature Award of 2003 ASP-DAC University LSI Design Contest (A nearest-Hamming-distance Search memory LSI) |
| Industrial and Nation-wide Cooperation |
・STARC Joint Research Member(2-thema, 2001-)
・Cooperative Researcher of VLSI Design and Education Center at The University of Tokyo (2001-) |
| Academic Society Activities |
・Program Committee of Asia and South Pacific Design Automation Conference (ASPDAC) (1997-2001, 2004), Program Committee of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI) (1997-2003), Associate Editor of Special Section on VLSI Design and CAD Algorithms, IEICE Trans. on Fundamentals (A) (1996-2002), Associate Editor, IEICE Trans. on Fundamentals (A) (1999-2003), Organizing Committee of IEICE Karuizawa Workshop on Circuits and Systems (1997-2001), Organizing Committee of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI) (2003-), Secretary of IEICE Chugoku Chapter (2002-), IPSJ SLDM Technical Group Member(2003-), Organizing Committee of 2004 IEEE International Midwest Symposium on Circuits and Systems (2003-) |
| Important Publications |
| 1. |
T. Morimoto,
Y. Harada, T. Koide, and H.-J. Mattausch: "Low-complexity,
highly-parallel color motion-picture segmentation
architecture for compact digital CMOS implementation",
Extended Abstracts of the 2002 International
Conference on Solid State Devices and Materials
(SSDM2002), pp.242-243, (2002). |
| 2. |
Y. Yano, T. Koide,
and H.-J. Mattausch: "Fully parallel nearest
Manhattan-distance-search memory with large reference-pattern
number", Extended Abstracts of the 2002
International Conference on Solid State Devices
and Materials (SSDM2002), pp.254-255, (2002). |
| 3. |
H.-J. Mattausch,
T. Gyohten, Y. Soda, T. Koide :"Compact
associative-memory architecture with fully-parallel
search capability for the minimum Hamming distance",
IEEE Journal of Solid-State Circuits, Vol. 37,
No.2, pp.218-227, February (2002). |
| 4. |
H.-J. Mattausch,
N. Omori, S. Fukae, T. Koide, T. Gyohten:"Fully-parallel
pattern-matching engine with dynamic adaptability
to Hamming or Manhattan distance", Proc.
of 2002 Symposium on VLSI Circuits , pp. 252-255,
June (2002). |
| 5. |
S. Yamasaki, S. Nakaya, S. Wakabayashi, and T. Koide: "A Performance-Driven Floorplanning Method with Interconnect Performance Estimation", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E85-A, No.12, pp. 2775-2784, (2002). |
| 6. |
T. Morimoto, Y. Harada, T. Koide and H.J. Mattausch, "Low-Power Real-Time Region-Growing Image-Segmentation in 0.35mm CMOS due to Subdivided-Image and Boundary-Active-Only Architectures," Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, pp. 146-147, (2003). |
| 7. |
T. Morimoto, Y. Harada, T. Koide, H. J. Mattausch, "Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation", IEIEC Trans. Inf. & Syst., Vol.E87-D, No.2, pp.500-503, (2004). |
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| Important Patent Apprications |
| 1. |
T. Koide, H.J. Mattausch, T. Morimoto, Y. Harada, "Picture Segmentation Method, Picture Segmentation Equipment, Real-Time Picture-Processing Method, Real-Time Picture-Processing Equipment and Picture-Processing Integration Circuit", Priority: 27.5.2002 (Japanese Patent Application No. 2002-152491) |
| 2. |
H.J. Mattausch, T. Koide, "Winner-Line-Up Amplifier with Self-Adapting Maximum-Gain Region", Priority: 31.5.2002 (Japanese Patent Application No. 2002-159436) |
| 3. |
H.J. Mattausch, T. Koide, "Pattern-Recognition System, Associative-Memory Equipment Contained in this System and Pattern-Recognition-Processing Method", Priority: 6.6.2002 (Japanese Patent Application No. 2002-165769) |
| 4. |
T. Koide, H.J. Mattausch, T. Morimoto, Y. Harada,"Picture Segmentation Equipment, Picture-Processing Method, and Picture-Processing Integration Circuit", Priority: 9.12.2002 (Japanese Patent Application No. 2003-322163) |
| 5. |
H.J. Mattausch, T. Koide, M. Mizokami, "Reference Pattern Recognition/Learning Method and Pattern Recognition System", Priority: 12.26.2003 (Japanese Patent Application No. 2003-434596) |
| 6. |
T. Koide, H.J. Mattausch, Y. Yano, "Minimum Manhattan-Distance Search Associative Memoriy Equipment", Priority: 1.26.2004 (Japanese Patent Application No. 2004-017429) |
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| Laboratory Page |
http://www.rcns.hiroshima-u.ac.jp/ |
| Personal Page |
http://www.rcns.hiroshima-u.ac.jp/koide/ |
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COE Program