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Profile |
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| Name and Affiliation |
Mitiko Miura-Mattausch
mmm hiroshima-u.ac.jp
Graduate School of Advanced Sciences of Matter
Hiroshima University
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| Education and Professional Background |
| 1996- |
Hiroshima University, Professor leading Ultra-Small Devices Engineering Laboratory |
| 1984-1996 |
Siemens AG, Senior Researcher at Central Research and Development Labs. |
| 1981-1984 |
Max-Planck-Institute, Researcher at Theoretical Solid-State Physics Laboratory |
| 1980.3 |
Dr. of Sciemnce, Hiroshima University |
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| Significant Contributions |
The development of the MOSFET model HiSIM (Hiroshima-university STARC IGFET Model) based on
the complete surface-potential description, and the source code and the manual have been
released under free license for the public since the end of 2001.
The device/model development for future, especially for RF-circuits, under collaborations
with other international affiliations.
The development of a device modeling approach for including the hot electron temperature
in a self-consistent way in 2-dimensional simulations, which was implemented into two
major device simulators (MINIMOS, GALENE) in the middle of the eighties.
The development of the 50GHz technology with bipolar transistors, realized large current
gain by improving the emitter/contact interface condition. |
| Awards |
2000: Best Paper Award of Asia South Pacific Design Automation Conference
“Correlation Method of Circuit-Performance and Technology Fluctuations for Improved Design Reliability”:
selected among 100 accepted papers
1998: Best Paper Award of Asia South Pacific Design Automation Conference
“Concurrent Technology, Device, and Circuit Development for EEPROMs”: selected among 100 accepted papers
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| Invited Presentations |
“Test Circuit for Extracting Sub-100nm MOSFET Technology Variations with the MOSFET Model HiSIM,”
Proc. Int. Conf. Microelectronic Test Structures (Awaji), March 2004.
“Noise Modeling with HiSIM Based on Self-Consistent Surface-Potential Description,”Proc. Modeling and
Simulation of Microsystems (Boston), March 2004.
“MOSFET Moldeing for RF-CMOS Design,” Proc. Asia South Pacific Design Automation Conf. (Yokohama),
pp. 482-490, Jan. 2004.
“HiSIM: Accurate Change Modeling Important for RF Era,”Proc. Modeling and Simulation of
Microsystems (San Francisco), Vol.2, pp. 258-261, Feb. 2003.
“HiSIM: A MOSFET model for circuit simulation connecting circuit performance with technology,”
Tech. Digest Int. Electron Devices Meeting (San Francisco), pp. 109-112, Dec. 2002.
“HiSIM:MOSFET-Model for Circuit Simulation with Self-Consistent surface Potential,”
Fabless-Semiconductor-Association Meeting (San Jose), Sept. 2002.
“HiSIM: Selft-Consistent Surface-Potential MOS-Model Valid Down to Sub-100nm Technologies,”
Proc. Modeling and Simulation of Microsystems (Puerto Rico), pp. 678-681, Apri. 2002.
“The 100nm-MOSFET Model HiSIM and Its Extension to RF Applications,”Int. Sym. Quality Electronic
Design (San Jose), March 2002.
“HiSIM: The First Complete Drift-Diffusion MOSFET Model for Circuit Simulation,”Proc. Int. Conf.
Solid-State & Integrated Circuit Technology (Shanghai), pp. 861-866, Oct. 2001.
“Circuit Simulation Models for Coming MOSFET Generations,” Proc. The 14th Workshop on Circuits
and Systems in Karuizawa, pp.317-322, April 2001.
“Circuit Simulation Models for Coming MOSFET Generations,” Proc. Int. Conf. Simulation Semicon.
Processes & Devices (Seattle), pp. 106-111, Sept. 2000.
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| Major Publications |
| 1. |
M. Miura-Mattausch, H. Ueno, H. J. Mattausch, K. Morikawa, S. Itoh, A. Kobayashi, and H. Masuda,
“100nm-MOSFET Model for Circuit Simulation: Challenges and Solutions,” IEIEC Trans. Electron., Vol. E86,
pp. 1009-1021, 2003. (invited) |
| 2. |
“High-Electric-Field Electron Transport at Silicon/Silicon-Dioxide Interface Inversion Layer,”
M. Tanaka, H. Ueno, O. Matsushima, and M. Miura-Mattausch Jpn., J. Appl. Phys., 42[3B], pp.L280-282,
2003.3. |
| 3. |
“Circuit-Simulation Model of Cgd Changes in Small-Size MOSFETs Due to High Channel-Field Gradients,”
D. Navarro, H. Kawano, K. Hisamitsu, T. Yamaoka, M. Tanaka, H. Ueno, M. Miura-Mattausch, H.J. Mattausch,
S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, IEICE Transactions on Electronics, E86-C[3],
pp.474-480, 2003.3. (invited)
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| 4. |
T. Okagaki, M. Tanaka,
H. Ueno, and M. Miura-Mattausch, "Importance
of Ballistic
Carriers for the Dynamic Response in Sub-100nm
MOSFETs," IEEE Electron Device
Letters, Vol. 23, No. 3, pp. 154-156, 2002. |
| 5. |
H. Ueno, D. Kitamaru, K. Morikawa, M. Tanaka, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T.
Yamaguchi,
K. Yamashita, and N. Nakayama, "Impurity-Profile-Based Threshold-Voltage Model of Pocket-Implanted MOSFETs
for Circuit Simulation,” IEEE Trans. Electron Devices, Vol. 49, pp. 1783-1789, 2002.
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| 6. |
H. Kawano, M. Nishizawa, S. Matsumoto, S. Mitani, M. Tanaka, N. Nakayama, H. Ueno, M. Miura-Mattausch, and
H. J. Mattausch, “A Practical Small-Signal Equivalent Circuit Model for RF-MOSFETs Valid up to the Cut-Off
Frequency,” IEEE Int. Microwave Symp. Digest, pp. 2121-2124, June 2002.
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| 7. |
S. Matsumoto, H. J. Mattausch, S. Ooshiro, Y. Tatsumi, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi,
K. Yamashita, and N. Nakayama, "Test-Circuit-Based Extraction of Inter- and Intra-Chip MOSFET-Performance
Variations for Analog-Design Reliability," Proc. Custom Integrated Circuit Conference, pp. 357-360, June
2001.
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| 8. |
M. Miura-Mattausch, M. Suetake, H. J. Mattausch, S. Kumashiro, N. Shigyo, S. Odanaka, and N. Nakayama,
Physical Modeling of the Reverse-Short-Channel Effetc for Circuit Simulation,” IEEE Trans. Electron
Devices,
Vol. 48, pp. 2449-2452, 2001.
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| 9. |
M. Miura-Mattausch, H. J. Mattausch, N. D. Arora, and C. Y. Yang, "MOSFET Modeling Gets Physical,"
IEEE Circuits and Devices, Vol. 17, pp. 29-36, 2001.
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| 10. |
“Physically-Based Threshold Voltage Determination for MOSFET’s of All Gate Lengths,” M. Tsuno, M. Suga,
M. Tanaka, K. Shibahara, M. Miura-Mattausch, and M. Hirose, IEEE Trans. Electron Devices, Vol. 46, No. 7,
pp. 1429-1434, July 1999. |
| 11. |
“Superstable Neutral Electron Traps in Nonplanar Thermal Oxides on Monocrystalline Silicon,” T. Ono,
M. Miura-Mattausch, H. Baumgaertner, and H. J. Mattausch, Appl. Phys. Letters, Vol. 76, No. 16, pp. 2298-
2300,
April 2000.
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| 12. |
T. Takahashi, M. Miura-Mattausch, and Y. Omura, "Transconductance Oscillations in MOSFET with Thin SOI
Originated by Quantized Energy, "App. Phys. Lett., Vol. 75, pp. 1458-1460, 1999. |
| 13. |
M. Miura-Mattausch, U. Feldmann, A. Rahm, M. Bollu, and D. Savignac, "Unified Complete MOSFET Model for
Analysis of Digital and Analog Circuits," IEEE Trans. CAD/ICAS, Vol. 15, pp. 1-7, Jan. 1996. |
| 14. |
W. Haensch and M. Miura-Mattausch, "The Hot-Electron Problem in Small Semiconductor Devices, " J. Appl.
Phys., Vol. 60, pp. 650-656, 1986.
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| 15. |
“Dependence of Current Gain beta on Spacer Geometry and Emitter Size in Polysilicon Self-Aligned Bipolar
Transistors,” M. Miura-Mattausch, J. Ruestig, and R. Kircher, Solid-State Electronics, Vol. 33, No. 3,
pp. 325-331, March 1990.
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| Books |
| 1. |
"Circuit-Simulation Technics and MOSFET Modeling," Sipec, 2003. |
| 2. |
"Ultra-Fast Silicon Bipolar Technology," Springer-Verlag, 1989. |
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| Laboratory Page |
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| Personal Page |
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COE Program