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Program of the 2nd Workshop

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Hiroshima Univ. Symposium

COE Seminar

COE Technical Meeting

The 2nd Hiroshima International Workshop on

Nanoelectronics for Terra-Bit Information Processing

The 21st century COE program "Nanoelectronics for Terra-Bit Information Processing" aims at fusion of silicon-based nanodevice, circuit and chip-architecture research for the basic construction of integrated systems with high-level recognition and learning functionality. Bringing up independent researches which are capable of advanced, visionary and well reflected research in a broad range of fields is our way to realize them.

Our main goals are:

* Unification of silicon-based system, circuit, device-modeling and device fabrication research

* Solution of the persistent 3-dimensional-integration problems by a wireless integration methodology

* Realization of integrated systems with high-level recognition and learning capabilities by innovative circuits and architectures

Within the scope of the COE program, we hold workshops in the framework of the COE program to demonstrate our progress, as well as to interact with worldwide leading groups for exchanging information as well as possible collaboration.

The first workshop was held on March 17th in 2003, presented overview of the focused fields in the COE. Presentations by outstanding leaders over the world were also given for proving our purpose and searching future interactions.

The 2nd workshop will be held

Date: January 30th, 2004 (9:00-18:00)

Place: Hiroshima University, Advanced Sciences of Matter, Room 401N

The 2nd workshop focuses on the modeling tasks of the COE, aiming at providing opportunity to get an overview of present activities undertaken in the world. Requirement for simulations is incerasing due to the complexity of device characteristics approaching technological limitation. More efforts are also requested to realize accurate SoC simulations. At the workshop possibility to realize tight collaborations among different fields to accelerate the achievement is also discussed.

Program (not yet confirmed)


A. Iwata   (10min.) Recent Progress of the COE

K. Ishibashi (STARC) (60min.) Low Power SoC Technology Development at STARC

Z. Yu (Tsinghua Univ.) (60min.) Ballistic MOS Model with Full 2D QM Correction

T. Kikkawa   (20min.) Wireless Interconnection on Si LSI using Integrated Antenna

G. Wachutka (TU Muenchen) (60min.) Physics-Based Modeling of Electro-Magnetic Parasitic

Effects in Interconnects

Lunch Break (12:30-14:00)

M. Chan (Hong Kong Univ. ST) (60min.) Modeling CMOS Non-Quasi-Static Effects in a Quasi-Static Simulation Engine

M. Miura-Mattausch (40min.) MOSFET Modeling for RF-CMOS Design

Poster Session (16:00-18:00)


Dinner (Cotton Club)


1. 1/f and Non-1/f Low Frequency Noise Measurements and their Modeling with HiSIM

H. Ueno, S. Matsumoto, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama

2. Toward Current-Characteristics Simulation for p-i-n Photodiodes Based on Spectral Method

K. Konno, O. Matsushima, K. Hara, G. Suzuki, and M. Miura-Mattausch

3. Optical properties of ring resonators on Si chips

Y. Tanushi, M. Wake, K. Wakushima, and S. Yokoyama

4. Etching Properties and Optical Emission Spectroscopy of NH3 Added C5F8 Pulse-Modulated ICP Plasma

M. Ooka and S. Yokoyama

5. Study in Structure and Fabrication Process of 3-Dimensional CMOS Transistor 

K. Okuyama, K. Kobayashi, and H. Sunami

6. Associative Memory for High-Speed Nearest Hamming/Manhattan Distance Search with

Large Reference Pattern Number

Y. Yano, T. Koide, H. J. Mattausch

7. Chip-architecture for automatic learning based on associative Memory and Short/Long Term Storage Concept

M. Mizokami, Y. Shirakawa, T. Koide, and H. J. Mattausch

8. Improved Mixed Digital-Analog Nearest-Match Circuit for Fully-Parallel Assosiative Memories

K. M. Rahman, K. Kamimura, T. Koide, and H. J. Mattausch

9. Low-Power Digital Image Segmentation of Real-Time VGA-Size Motion Pictures

T. Morimoto, Y. Harada, O. Kiriyama, H. Adachi, T. Koide, and H. J. Mattausch

10. Multiple-Step Electron Charging in Si Quantum-Dot Floating Gate nMOSFETs

M. Ikeda, Y. Shimizu, T. Shibaguchi, H. Murakami, and S. Miyazaki.

11. Electronic Charged States of Single Si Quantum Dots with Ge Core as Detected by an AFM/Kelvin Probe Technique

Y. Darma, K. Takeuchi, and S. Miyazaki

12. Local Characterization of Electronic Transport in Microcrystalline Germanium Thin Films by Atomic Force Microscopy Using a Conducting Probe

K. Makihara, Y. Okamoto, H. Nakagawa, M. Ikeda, H. Murakami and S. Miyazaki

13. Workfunction Tuning for Single-Metal Dual-Gate with Mo and NiSi Electrodes

T. Sano, M. Hino, and K. Shibahara

14. Wireless Chip Interconnect Using Resonant Coupling between Spiral Inductors

M. Sasaki, D. Arizono, and A. Iwata

15. Human Face Detection and Recognition Using Principle Component Analysis

H. Ando, N. Fuchigami, M. Sasaki, and A. Iwata

16. A Multi-chip Vision System with a PWM-based Line Parallel Interconnection

S. Kameda, M. Sasaki, and A. Iwata

17. Neural Sensing LSI with Wireless Interface

T. Yoshida, T. Mashimo, M. Akagi, and A. Iwata

18. CDMA Communication Chips for Highly Flexible Robot Brain

M. Shiozaki, T. Mukai, M. Sasaki, and A. Iwata

19. A Strategy Learning Model for Robot Brain

M. Ono, M. Sasaki, and A. Iwata

20. A Single Chip UWB Transmitter based on 0.18μm CMOS Technology for Wireless Interconnection

P. K. Saha, N. Sasaki, and T. Kikkawa

21. A Single Chip UWB Receiver based on 0.18μm CMOS Technology for Wireless Interconnection

N. Sasaki, P. K. Saha, and T. Kikkawa

22. Atomic layer deposition of HfO2 for gate dielectrics

Y. Yokoyama, H. Ishii, and A. Nakajima