日時：平成15年1月27日（月）、13：10-14：30

場所：ナノデバイス・システム研究センター　東棟5階会議室

講演題目：Breakdown and Reliability of Ultra-Thin MOS Devices

講演者：J. Sune*
*Department d’Enginyeria Electronica., Universitat Autonoma de Barcelona. Bellaterra, SPAIN

共同研究者：Y. Wu, W. L. Lai and D. Jimenez*
IBM Microelectronics Division. Essex Junction (VT), USA

講演内容：
Silicon dioxide based dielectrics in the 1 nm thickness range remain the first-choice candidate as gate insulators for sub-100nm CMOS technology while much research on alternative high-K materials is being conducted. Therefore, the reliability of these ultra-thin oxide films is still a subject of great interest. For reliability predictions based on the occurrence of the first breakdown (BD), the methodology must be based on coupling the dynamics of defect generation to a physics-based model for the BD statistics. The scaling of the MOSFET and the associated reduction of the oxide thickness leads to an important reduction of reliability margin due to the reduced defect density required for the breakdown, the increased leakage due to direct tunneling and the degradation of the Weibull slope. Fortunately, however, the first breakdown might not always be the best definition of device failure because some MOS digital circuits remain functional after BD provided that the post-breakdown gate leakage is low enough. Hence, at least for some applications, several BD events can be tolerated before device or chip failure and this gives additional reliability margin. In this framework, a lot of issues related to the detailed description of the BD phenomenon in ultra-thin oxides have arisen. Device failure criteria have to be defined at the device level and also at the chip level, current supply limitation in the circuit environment can play a relevant role, progressive evolution of the current after Hard Breakdown (HBD) can give an additional reliability margin, etc. Further understanding of the post-breakdown phenomenology is required to integrate all these observations into an application-specific reliability methodology.

In this work, we concentrate on two descriptions of the tolerance of device or circuits to breakdown events which can be useful for future reliability assessment methodology. First, we consider the existence of two breakdown modes, SBD and HBD, with prevalence ratios that depend on gate voltage. We study the statistics of SBD and HBD and their relation to the statistics of the first BD event as a function of their prevalence ratios. We also briefly consider the modeling of the BD runaway in terms of energy dissipation in a first-order attempt to obtain the prevalence ratios as a function of stress conditions and device geometry. Second, we deal with the description of the statistics of successive BD events. This is the basis to deal with applications which can tolerate a fixed number of BD events without failure.