Publications and Patents of H.J. Mattausch

Other Publications and Patents of Hans Juergen Mattausch

[I] Doktor Thesis

Vielteilchentheoretische Beschreibung des elektronischen Systems perfekter und gestoerter kovalenter Kristalle am Beispiel von Diamant und Silizium
(Many-particle description of the electronic system of perfect and disturbed covalent crystals for the examples of diamond and silicon)

University of Stuttgart (Germany) 29.5.1981

[II] Publications in Journals and Books

1. H.J. Mattausch and Ch. Uihlein, "Multiplet structure of p-excitons in CuBr due to valence band degeneracy", Solid State Communications, 25, 447-449 (1978)

2. H.J. Mattausch and Ch. Uihlein, "Fine structure of p-excitons in CuBr", physica status solidi (b) 96, 189-200 (1979)

3. G. Strinati, H.J. Mattausch and W. Hanke, "Dynamical correlation effects on the quasiparticle Bloch states of covalent crystals", Physical Review Letters 45, 290-294 (1980)

4. G. Strinati, H.J. Mattausch and W. Hanke, "First-principle calculation of self-energy corrections in covalent crystals", Journal of the Physical Society of Japan 49 Supplement A, 77-80 (1980)

5. W. Hanke, G. Strinati and H.J. Mattausch, "Dynamical correlation effects on the one-electron states of covalent crystals", In "Recent Developments in Condensed Matter Physics", Vol. 1, edited by J.T. Devreese (Plenum, New York, 1981), p. 263-279

6. H.J. Mattausch and D.E. Aspnes, "Optical properties of InSb and its electrochemically grown anodic oxide", Physical Review B23, 1896-1901 (1981)

7. G.Strinati, H.J. Mattausch and W. Hanke, "Dynamical aspects of correlation corrections in a covalent crystal", Physical Review B25, 2867-2888 (1982)

8. H.J. Mattausch, W. Hanke and G. Strinati, "Many-body effects in the screening of substitutional impurities in covalent crystals", Physical Review B26, 2302-2305 (1982)

9. H.J. Mattausch, W. Hanke and G. Strinati, "Impurities in covalent crystals: Exchange-correlation and local-field effects", Physical Review B27,3735-3747 (1983)

10. W. Hanke, H.J. Mattausch and G. Strinati, "Theory of exchange-correlation effects in the electronic single- and two-particle excitations of covalent crystals", In "Electron correlations in solids, molecules and atoms", edited by J.T. Devreese (Plenum, New York, 1983), S. 289-360

11. H.J. Mattausch, B. Hasler and W. Beinvogl, "Reactive ion etching of Ta-Silicide/Polysilicon double layers for the fabrication of integrated circuits", Journal of Vacuum Science and Technology B1, 15-22 (1983)

12. N. Meskini, H.J. Mattausch and W. Hanke, "Many-body effects in the absorption spectrum of a heteropolar crystal", Solid State Communications 48, 807-809 (1983)

13. W. Hanke, Th. Goelzer and H.J. Mattausch, "Exchange-Correlation Potential for One-Electron Excitations in a Semiconductor", Solid State Communications 51, 23-26 (1984)

14. N. Meskini, W. Hanke, H.J. Mattausch, M. Balkanski and M. Zouaghi, "The absorption spectrum of a heteropolar crystal - the role of many-particle effects", J. Phys.(France) 45, 1707-1715 (1984)

15. B. Zehner, H.J. Mattausch, F. Matthiesen, R.Tielert and H.J. Grallert, "A CMOS VLSI Chip for Filtering of TV Pictures in Two Dimensions", IEEE Journal of Solid-State Circuits, Vol. sc-21,No. 5, 797-802 (1986)

16. H.J. Mattausch, F. Matthiesen, J. Haertl, R. Tielert and E.P. Jacobs, "A Memory-Based High-Speed Digital Delay Line with a Large Adjustable Length", IEEE Journal of Solid-State Circuits, Vol. sc-23, No. 1, 105-110, (1988)

17. H. Brunner, Y.C. Gerstenmaier and H.J. Mattausch, "Impact of cell geometries and electrothermal effects on IGBT latch-up in 2d-simulation", In "Simulation of Semiconductor Devices und Processes", Vol.5, edited by S. Selberherr, H. Stippel, E. Strasser, Springer-Verlag, 45-48 (1993)

18. H.J. Mattausch, M. Kerber, R. Allinger and H. Braun, "Localized highly stable electrical passivation of the thermal oxide on nonplanar polycrystalline silicon", Appl. Phys. Lett. 71, 3391-3393 (1997)

19. R. Kraus and H.J. Mattausch, "Status and Trends of Power Semiconductor Device Models for Circuit Simulation", IEEE Trans. on Power Electronics 13, 452-465 (1998)

20. H.J. Mattausch and K. Yamada, "Application of Port-Access-Rejection Probability Theory for Integrated N-Port Memory Architecture Optimization", IEE Electronics Letters 34, 861-862 (1998)

21. H.J. Mattausch, R. Allinger, M. Kerber and H. Braun, "A Degradation Mechanism of EEPROM Cell Operational Margins which Remains Undetected by Conventional Quality Assurance", IEEE Electron Device Letters 19, 402-404 (1998)

22. H.J. Mattausch, "Hierarchical architecture for area-efficient integrated N-port memories with latency-free multi-gigabit per second access bandwidth", IEE Electronics Letters 35, 1441-1443 (1999)

23. Y. Tatsumi and H.J. Mattausch, "Fast quadratic increase of multiport-storage-cell area with port number", IEE Electronics Letters 35, 2185-2187 (1999)

24. H.J. Mattausch, H. Baumgaertner, R. Allinger, M. Kerber and H. Braun, "Electrical/Thermal Properties of Nonplanar Polyoxides and the Consequent Effects for EEPROM Cell Operation", IEEE Trans. on Electron Devices 47, 1251-1257 (2000)

25. T. Ono, M. Miura-Mattausch, H. Baumgaertner and H. J. Mattausch, "Super-stable neutral electron traps in nonplanar thermal oxides on monocrystalline silicon", Appl. Phys. Lett. 76, 2298-2300 (2000)

26. H.J. Mattausch, K. Kishi and T. Gyohten, "Area-efficient multi-port SRAMs for on-chip data-storage with high random-access bandwidth", IEICE Trans. on Electronics, vol. E84-C, 410-417 (2001)

27. N. Omori and H.J. Mattausch, "Compact central arbiters for memories with multiple ports", IEE Electronics Letters 37, 811-813 (2001)

28. M. Miura-Mattausch, M. Suetake, H.J. Mattausch, S. Kumashiro, N. Shigyo, S. Odanaka, and N. Nakayama, "Physical Modeling of the Reverse-Short-Channel Effect for Circuit Simulation", IEEE Trans. on Electron Devices 48, 2449-2452 (2001)

29. M. Miura-Mattausch, H.J. Mattausch, N. D. Arora, and C. Y. Yang, "MOSFET Modeling Gets Physical", IEEE Circuits and Devices Magazine 17 (6), 29-36 (2001)

30. H.J. Mattausch, T. Gyohten, Y. Soda and T. Koide, "Compact Associative-Memory Architecture with Fully-Parallel Search Capability for the Minimum Hamming Distance", IEEE Journal of Solid-State Circuits, 37, 218-227, (2002)

31. M. Miura-Mattausch, H. Ueno, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Circuit Simulation Models for Coming MOSFET Generations", IEICE Trans. Fundamentals, vol. E85-A, no. 4, 740-748 (2002)

32. K. Morikawa, H. Ueno, D. Kitamaru, M. Tanaka, T. Okagaki, M. Miura-Mattausch, H.J. Mattausch, S, Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Quantum Effect in Sub-100nm MOSFET with Pocket Technologies and its Relevance for the On-Current Condition", Jpn. J. Appl. Phys. 41, 2359-2362 (2002)

33. H. J. Mattausch, M. Suetake, D. Kitamaru, M. Miura-Mattausch, S. Kumashiro, N. Shigyo, S. Odanaka and N. Nakayama, "Simple nondestructive extraction of the vertical channel-impurity profile of small-size metal-oxide-semiconductor-field-effect transistors", Appl. Phys. Lett. 80, 2994-2996 (2002)

34. H. Ueno, D. Kitamaru, K. Morikawa, M. Tanaka, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Impurity-Profile-Based Threshold-Voltage Model of Pocket-Implanted MOSFETs for Circuit Simulation", IEEE Trans. on Electron Devices 49, 1783-2996 (2002)

35. S. Matsumoto, K. Hisamitsu, M. Tanaka, H. Ueno, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka, and N. Nakayama, "Validity of the mobility universality for scaled metal-oxide-semiconductor field-effect transistors down to 100nm gate length", J. Appl. Phys. 92, 5228-5232 (2002)

[III] Publications at Conferences

36. H.J. Mattausch and Ch. Uihlein, "Feinstruktur der P-Exzitonen in CuBr", Proceedings of the Spring meeting of the German Physical Society (DPG), 65 (1978)

37. G. Strinati, H.J. Mattausch and W. Hanke, "First-principles calculation of self-energy corrections in covalent crystals", Proceedings of the Spring meeting of the German Physical Society (DPG), 157 (1980)

38. H.J. Mattausch, G. Strinati and W. Hanke, "Vielteilcheneffekte in der Abschirmung einer Stoerstelle in einem kovalenten Kristall", Proceedings of the Spring meeting of the German Physical Society (DPG), 186 (1980)

39. G. Strinati, H.J. Mattausch and W. Hanke, "First-principle calculation of self-energy corrections in covalent crystals", Proceedings of the 15th International Conference on the Physics of Semiconductors, Kyoto, Japan, Sept. 1-9, 1980, 77-80 (1980)

40. H.J. Mattausch, T. Goelzer and W. Hanke, "Dynamische Korrelationseffekte im Quasiteilchenspectrum von Silizium", Proceedings of the Spring meeting of the German Physical Society (DPG), 693 (1982)

41. M. Cardona, H.J. Mattausch and L. Vina, "Bestimmung der optischen Konstanten von Halbleitern mit einem automatischen Ellipsometer", Proceedings of the Spring meeting of the German Physical Society (DPG), 697 (1982)

42. B.K. Bose, H.J. Mattausch and B. Schallenberger, "VLSI design considerations for Smalltalk on a RISC (SOAR)", Proceedings of CS292R "Smalltalk on a RISC", Department of Electrical Engineering and Computer Science, UC Berkeley 1983, p. 42-63

43. B. Zehner, H.J. Mattausch, R. Tielert and H.J. Grallert, "A CMOS Two-Dimensional Digital Filter for TV Pictures", ISSCC Digest of Technical Papers, 146-147 (1986)

44. H.J. Mattausch, F. Matthiesen, J. Haertl and E.P. Jacobs, "A Memory-Based, Arbitrarily Adjustable CMOS Digital Delay Line", 1987 Symposium on VLSI Circuits Digest of Technical Papers, 21-22 (1987)

45. B. Zehner, H.J. Mattausch, F. Matthiesen, M. Schoebinger, R. Tielert, H. Klar and K.H. Moehrmann, "Video chip set for data rate compression by filtering and DPCM Coding", Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS), Helsinki 1988, 697-700 (1988)

46. D. Schmitt-Landsiedel, G. Neuendorf, B. Hoppe and H.J. Mattausch, "Hierarchical Architecture for fast CMOS SRAMs", Proceedings of COMP EURO 89, VLSI and Computer Peripherals, 1-32 bis 1-34 (1989)

47. P.Tuerkes and H.J. Mattausch, "A new generation of circuit simulators makes power MOSFET models simple", Proceedings of the Symposium on Materials and Devices for Power Electronics (EPE-MADEP) 1991, 276-279 (1991)

48. R. Kraus, P. Tuerkes and H.J. Mattausch, "Modelling the self-heating of power devices", Proceedings of the 4th International Symposium on Power Semiconductor Devices & ICs (ISPSD 92), 124-129 (1992)

49. R. Kraus, K. Hoffmann and H.J. Mattausch, "A precise model for the transient characteristics of power diodes", Poceedings 23rd Annual IEEE Power Electronics Specialists Conference (PESC 92), 863-869 (1992)

50. H. Brunner, H.J. Mattausch and H. Mitlehner, "2D-Simulations of the surge current and reverse recovery behaviour of fast power diodes", Proceedings of the International Seminar on Power Semiconductors (ISPS 92), 11-17 (1992)

51. H. Brunner and H.J. Mattausch, "A new figure of merit for fast power diodes and a comparison with 2D-simulations", Proceedings: 6. Internationale Konferenz Leistungshalbleiter and ihre Anwendungen, electronica 92, Muenchener Messe- and AusstelLungsgesellschaft mbH, 9-16 (1992)

52. H. Conrad, M. Cotorogea and H.J. Mattausch, "Modellierung des Non-Punch-Through (NPT-) IGBT fuer die Netzwerksimulation", Proceedings: 6. Internationale Konferenz Leistungshalbleiter and ihre Anwendungen, electronica 92, Muenchener Messe- and Ausstellungsgesellschaft mbH, 37-47 (1992)

53. H. Goebel, R. Kraus and H.J. Mattausch, "A hybrid-method for modeling semiconductor power devices", Poceedings 24th Annual IEEE Power Electronics Specialists Conference (PESC 93), 45-52 (1993)

54. C.L. Ma, P.O. Lauritzen, P. Tuerkes and H.J. Mattausch, "A physically-based lumped-charge SCR model", Poceedings 24th Annual IEEE Power Electronics Specialists Conference (PESC 93), 53-59 (1993)

55. Y.C. Gerstenmaier and H.J. Mattausch, "Hochvolt-IGBT-Simulationen und Kriterium fuer optimale Sperrspannungs-Dimensionierung", Proceedings: 22. Kolloquium Halbleiter-Leistungsbauelemente und Materialguete, 1-4 (1994)

56. R. Allinger, M. Kerber, H.J. Mattausch and H. Braun, "Unexpected charge losses from the floating gates of EEPROM memory cells", Records of the 1996 IEEE International Workshop for Memory Technology, Design and Testing, Singapore, August 13-14, 92-98 (1996)

57. H.J. Mattausch, "Hierarchical N-Port Memory Architecture based on 1-Port Memory Cells", Proceedings of the 23rd European Solid-State Circuits Conference (ESSCIRC'97), Southampton, UK, September 16-18, 348-351 (1997)

58. K. Yamada, H. Lee, T. Murakami and H.J. Mattausch, "A new multiport memory architecture exploiting a hierarchy of 1-port memory cell blocks", Proceedings of the 1998 IEICE (Institute of Electronics, Information and Communication Engineers) General Conference, Electronics, 215, (1998) (in Japanese)

59. H. Lee, T. Murakami, K. Yamada and H.J. Mattausch, "Novel logic circuits for conflict management in multiport memories", Proceedings of the 1998 IEICE (Institute of Electronics, Information and Communication Engineers) General Conference, Electronics, 216, (1998) (in Japanese)

60. K. Yamada, H. Lee, T. Murakami and H.J. Mattausch, "An Area-Efficient Circuit Concept for Dynamical Conflict Management of N-Port Memories with Multi-GBit/s Access Bandwidth", Proceedings of the 24th European Solid-State Circuits Conference (ESSCIRC'98), The Hague, Netherlands, September 22-24, 140-143 (1998)

61. T. Tatsumi and H.J. Mattausch, "On the necessity of drastically improved N-port-memory-area efficiency to enable Tb/s-bandwidth systems", Proceedings of the 1999 IEICE (Institute of Electronics, Information and Communication Engineers) General Conference, Electronics, 178, (1999) (in Japanese)

62. K. Kishi, T. Gyoten, Y. Tatsumi, K. Yamada and H.J. Mattausch, "Development of an area-efficient 4-port memory by exploiting a new hierarchical architecture (Hierarchy Level 1)", Proceedings of the 1999 IEICE (Institute of Electronics, Information and Communication Engineers) General Conference, Electronics, 179, (1999) (in Japanese)

63. T. Gyoten, K. Kishi, Y. Tatsumi, K. Yamada and H.J. Mattausch, "Development of an area-efficient 4-port memory by exploiting a new hierarchical architecture (Hierarchy Level 2)", Proceedings of the 1999 IEICE (Institute of Electronics, Information and Communication Engineers) General Conference, Electronics, 180, (1999) (in Japanese)

64. H.J. Mattausch, Y. Tatsumi, K. Kishi, T. Gyoten, and K. Yamada, "Aera-Efficient Multiport Memories for the Tb/s Bandwidth Era", Proceedings of the 25th European Solid-State Circuits Conference (ESSCIRC'99), Duisburg, Germany, September 21-23, 126-129 (1999)

65. M. Suetake, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, N. Shigio, S. Odanaka, and N. Nakayama, "Precise Physical Modeling of the Reverse-Short-Channel Effect for Circuit Simulation", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99), 207-210 (1999)

66. T. Ono, M. Miura-Mattausch, H. Baumgaertner, and H.J. Mattausch, "Deep neutral oxide traps near midgap at the corners of nonplanar MOS-capacitors", Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials (SSDM'99), 532-533 (1999)

67. M. Tanaka, N. Tokida, T. Okagaki, M. Miura-Mattausch, W. Hansch, and H.J. Mattausch, "High performance of short-channel MOSFETs due to an elevated central-channel doping", Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'2000), 365-370 (2000)

68. K. Kishi, T. Gyoten, Y. Tatsumi, J.S. Kim and H.J. Mattausch, "Development of area-efficient multiport memories for enabling Tbit/s bandwidth systems", Proceedings of the 2000 IEICE (Institute of Electronics, Information and Communication Engineers) General Conference, Electronics, C-12-69, 164, (2000) (in Japanese)

69. N. Omori, K. Kishi, T. Gyoten and H.J. Mattausch, "Design of conflict resolve circuits for hierarchical multiport memories with large port numbers", Proceedings of the 2000 IEICE (Institute of Electronics, Information and Communication Engineers) General Conference, Electronics, C-12-70, 165, (2000) (in Japanese)

70. Y. Tatsumi, S. Nara, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka and N. Nakayama, "Test circuits for verifying MOSFET models (1) -Subthreshold region-", Proceedings of the 2000 IEICE (Institute of Electronics, Information and Communication Engineers) General Conference, Electronics, A-1-44, 44, (2000) (in Japanese)

71. S. Nara, Y. Tatsumi, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka and N. Nakayama, "Test circuits for verifying MOSFET models (2) -Amplification of small input-voltage changes-", Proceedings of the 2000 IEICE (Institute of Electronics, Information and Communication Engineers) General Conference, Electronics, A-1-45, 45, (2000) (in Japanese)

72. K. Suematsu, N. Nagakura, M. Suetake, H.J. Mattausch, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka and N. Nakayama, "Modeling of poly depletion and quantum effects for MOSFETs", Proceedings of the 47th General Conference of the Japan Society of Applied Physics, 29p-YE-4, 61, (2000) (in Japanese)

73. N. Nagakura, K. Suematsu, M. Suetake, H.J. Mattausch, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka and N. Nakayama, "Conservation of mobility universality in the circuit simulation model HiSIM", Proceedings of the 47th General Conference of the Japan Society of Applied Physics, 29p-YE-2, 60, (2000) (in Japanese)

74. M. Suetake, K. Suematsu, H. Nagakura, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka and N. Nakayama, "HiSIM: A drift-diffusion-based advanced MOSFET model for circuit simulation with easy parameter extraction", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2000), 261-264 (2000)

75. N. Omori, K. Kishi, T. Gyohten, J. Kim and H.J. Mattausch, "Fast and Compact Central Arbiter for High Access-Bit-Rate Multi-Port Caches", Extended Abstracts of the 2000 International Conference on Solid State Devices and Materials (SSDM'2000), 360-361 (2000)

76. K. Kishi, T. Gyohten, J. Kim, H.J. Mattausch, Y. Tatsumi and S. Nara, "Super-Compact Shared-Cache Memories with Low Power Consumption for Multi-Issue Single-Chip Processors", Proceedings of the 26th European Solid-State Circuits Conference (ESSCIRC'2000), Stockholm, Sweden, September 19-21, 340-343 (2000)

77. D. Miyawaki, S. Matsumoto, H.J. Mattausch, S. Ooshiro, M. Suetake, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Correlation Method of Circuit-Performance and Technology-Fluctuations for Improved Design Reliability", Best-Paper Award, Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'2001), 39-44 (2001), Best Paper Award

78. H.J. Mattausch, T. Gyohten, Y. Soda and T. Koide, "An Architecture for Compact Associative Memories with Deca-ns Nearest-Match Capability up to Large Distances", IEEE International Solid-State Circuits Conference Digest of Tech. Papers (ISSCC'2001), 170-171 (2001)

79. S. Matsumoto, H.J. Mattausch, S. Ooshiro, Y. Tatsumi, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Test-Circuit-Based Extraction of Inter- and Intra-Chip MOSFET-Performance Variations for Analog-Design Reliability", IEEE Custom Integrated Circuits Conference (CICC'2001), 357-360 (2001)

80. N. Gyohten, Y. Soda, T. Koide and H.J. Mattausch, "Development of Compact and High-Speed Associative Memories with Nearest-Match Capability for Hamming Distance", Proceedings of the 2001 IEICE (Institute of Electronics, Information and Communication Engineers) General Conference, Electronics, C-12-38, 133, (2001) (in Japanese)

81. T. Honda, D. Kitamaru, M. Tanaka, H. Ueno, K. Morikawa, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Modeling and analysis of Pocket Implanted MOSFETs", Proceedings of the 48th General Conference of the Japan Society of Applied Physics, 28p-YA-7, 42, (2001) (in Japanese)

82. D. Kitamaru, H. Ueno, K. Morikawa, M. Tanaka, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Vth-Model of Pocket-Implant MOSFETs for Circuit Simulation", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2001), 392-395 (2001)

83. T. Koide, T. Gyohten, Y. Soda, H. J. Mattausch, "Architecture for Compact and Fast Associative-Memories with All-Parallel Nearest-Match Hamming-Distance Search", Technical Report of the IEICE (Institute of Electronics, Information and Communication Engineers), ICD2001-5(2001-04), 27-34, (2001) (in Japanese)

84. K. Morikawa, H. Ueno, D. Kitamaru, M. Tanaka, T. Okagaki, M. Miura-Mattausch, H.J. Mattausch, S, Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Enhanced Quantum Effect for Sub-100nm Pocket Technologies and its Relevance for the On-Current Condition", Extended Abstracts of the 2001 International Conference on Solid State Devices and Materials (SSDM'2001), 384-385 (2001)

85. H.J. Mattausch, M. Miura-Mattausch, H. Ueno, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "HiSIM: The First Complete Drift-Diffusion MOSFET Model for Circuit Simulation", Proceedings of the International Conference on Solid-State and Integrated-Circuit Technology (ICSICT'2001), 861-866 (2001), Invited Paper

86. K. Hisamitsu, K. Mizoguchi, M. Tanaka, H. Ueno, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Analysis of Temperature Dependence of Ring Oscillator for CMOS Low Voltage Application", Proceedings of the 48th General Conference of the Japan Society of Applied Physics, 28p-ZC-2, 42, (2002) (in Japanese)

87. H. Ueno, M. Miura-Mattausch, H. J. Mattausch, "Parameter Extraction and Development of Equivalent Circuit Model for Sub-100nm Devices", Technical Report of the Japan Society of Applied Physics, STM01-04 (2001-10), 20-25, (2001) (in Japanese)

88. H. Kawano, M. Nishizawa, S. Matsumoto, S. Mitani, M. Tanaka, N. Nakayama, H. Ueno, M. Miura-Mattausch and H.J. Mattausch, "A Practical Small-Signal Equivalent Circuit Model for RF-MOSFETs Valid up to the Cut-Off Frequency", Proceedings of the IEEE International Microwave Symposium (IMS'2002), 2121-2124 (2002)

89. H.J. Mattausch, N. Omori, S. Fukae, T. Koide and T. Gyohten, "Fully-Parallel Pattern-Matching Engine with Dynamic Adaptability to Hamming or Manhattan Distance", 2002 Symposium on VLSI Circuits Digest of Technical Papers, 252-255 (2002)

90. M. Miura-Mattausch, H. Ueno, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "HiSIM: Self-Consistent Surface-Potential MOS-Model Valid Down to Sub-100nm Technologies", Proceedings of the IEEE International Conference on Modeling and Simulation of Microsystems (MSM'2002), 678-681 (2002), Invited Paper

91. D. Navarro, K. Hisamitsu, T. Yamaoka, M. Tanaka, H. Kawano, H. Ueno, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Circuit-Simulation Model of Gate-Drain-Capacitance Changes in Small-Size MOSFETs Due to High Channel-Field Gradients", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2002), 51-54 (2002)

92. H. Ueno, S. Jinbou, H. Kawano, K. Morikawa, N. Nakayama, M. Miura-Mattausch and H.J. Mattausch, "Drift-Diffusion-Based Modeling of the Non-Quasistatic Small-Signal Response for RF-MOSFET Applications", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2002), 71-74 (2002)

93. T. Koide, T. Morimoto, Y. Harada and H.J. Mattausch, "Digital Gray-Scale/Color Image-Segmentation Architecture for Cell-Network-Based Real-Time Applications", Proceedings of the 2002 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'2002), 670-673 (2002)

94. T. Morimoto, Y. Harada, T. Koide and H.J. Mattausch, "Real-Time Segmentation Architecture of Gray-Scale/Color Motion Pictures and Digital Test-Chip Implementation", Proceedings of the 2002 IEEE Asia-Pacific Conference on ASICs (AP-ASIC'2002), 237-240 (2002)

95. T. Morimoto, Y. Harada, T. Koide and H.J. Mattausch, "Low-Complexity, Highly-Parallel Color Motion-Picture Segmentation Architecture for Compact Digital CMOS Implementation", Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials (SSDM'2002), 242-243 (2002)

96. Y. Yano, T. Koide and H.J. Mattausch, "Fully Parallel Nearest Manhattan-Distance-Search Memory with Large Reference-Pattern Number", Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials (SSDM'2002), 254-255 (2002)

97. S. Jinbou, H. Ueno, H. Kawano, K. Morikawa, N. Nakayama, M. Miura-Mattausch and H.J. Mattausch, "Analysis of Non-Quasistatic Contribution to Small-Signal Response for Deep Sub-Micron MOSFET Technologies", Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials (SSDM'2002), 26-27 (2002)

98. M. Miura-Mattausch, H. Ueno, M. Tanaka, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "HiSIM: A MOSFET Model for Circuit Simulation Connecting Circuit Performance with Technology", Proceedings of the 2002 IEEE International Electron Devices Meeting (IEDM'2002), 109-112 (2002), Invited Paper

99. T. Morimoto, Y. Harada, T. Koide and H.J. Mattausch, "Gray-Scale/Color Image-Segmentation Architecture based on Cell-Network", Technical Report of the IEICE (Institute of Electronics, Information and Communication Engineers), CAS2002-34, VLD2002-48, DSP2002-74 (2002-06), 49-54, (2002) (in Japanese)

100. T. Inoue, T. Sasaki, T. Hironaka, T. Koide and H.J. Mattausch, "A study of compact and multi-bank memory suitable for LSI", Technical Report of the IEICE (Institute of Electronics, Information and Communication Engineers), CAS2002-34, VLD2002-48, DSP2002-74 (2002-06), 125-130, (2002) (in Japanese)

101. H. Uchida, Y. Mitani, H.J. Mattausch, T. Koide and T. Hironaka, "Small-Area Multi-Port Register Files due to Bank Structure for Highly Parallel Processors", Technical Report of the IEICE (Institute of Electronics, Information and Communication Engineers), CAS2002-34, VLD2002-48, DSP2002-74 (2002-06), 31-36, (2002) (in Japanese)

102. S. Fukae, N. Omori, H.J. Mattausch, T. Koide, T. Inoue and T. Hironaka, "Comparison of the Hierarchical and Crossbar-based Architectures for the Construction of Multibank Multiport Memory", Technical Report of the IEICE (Institute of Electronics, Information and Communication Engineers), CAS2002-34, VLD2002-48, DSP2002-74 (2002-06), 37-42, (2002) (in Japanese)

103. T. Koide, H.J. Mattausch, N. Omori, S. Fukae, and T. Gyohten, "Pattern-Matching Engine Adaptable to Hamming or Manhattan Distance with Fully-Parallel Processing Capability", Technical Report of the IEICE (Institute of Electronics, Information and Communication Engineers), ICD2002-42 (2002-07), 41-46, (2002)

[IV] Patents

granted

104. H.J. Mattausch, "Integrierte Halbleiterschaltung in komplementaerer Schaltungstechnik mit Uberspannungsschutz-Struktur", Priority: 28.9.84, Granted: (DE3435751 Germany/18.7.1991)

105. H.J. Mattausch, "Schaltungsanordnung mit einer matrixfoermigen Speicheranordnung zur variabel einstellbaren Verzoegerung digitaler Signale (Nr. 1)", Priority: 4.9.85, Granted: (US4748595 USA/31.5.1988; EP213584B1 Europe/2.12.1992)

106. H.J. Mattausch, "Schaltungsanordnung mit einer matrixfoermigen Speicheranordnung zur variabel einstellbaren Verzoegerung digitaler Signale (Nr. 2)", Priority: 4.9.85, Granted: (US4691302 USA/1.9.1987; EP217122B1 Europe/5.6.1991)

107. H.J. Grallert and H.J. Mattausch, "Codierer fuer mehrdimensionale Differenz-Pulscode-Modulation mit hoher Arbeitsgeschwindigkeit (Nr. 1)", Priority: 23.9.85, Granted: (EP218917B1 Europe/16.8.1989)

108. H.J. Grallert and H.J. Mattausch, "Codierer fuer mehrdimensionale Differenz-Pulscode-Modulation mit hoher Arbeitsgeschwindigkeit (Nr. 2)", Priority: 23.9.85, Granted (EP218918B1 Europe/29.11.1989)

109. H.J. Mattausch, "Halbleiterspeicher mit wahlfreiem Zugriff fuer zwei getrennte Ports", Priority: 23.1.87, Granted: (US4860263 USA/22.8.1989; EP275884B1 Europe/26.5.1993)

110. K. Althoff, H.J. Mattausch and G. Neuendorf, "Leseverstaerker fuer statische Speicher in CMOS Technologie", Priority: 18.8.87, Granted: (JP01067795A2 Japan/14.3.1989; US5012450 USA/30.4.1991; EP303815B1 Europe/22.9.1993)

111. H.J. Mattausch, "Halbleiterspeicher mit einer Signalwechsel-Erkennungsschaltung", Priority: 18.8.87, Granted: (JP01066896A2 Japan/13.3.1989; US4924443 USA/8.5.1990; EP304591B1 Europe/3.3.1993)

112. H.J. Mattausch, F. Matthiesen, M. Schoebinger, "Anordnung zur DPCM-Codierung mit hoher Datenrate", Priority: 14.6.88, Granted: (JP02033288A2 Japan/2.2.1990; US4893184 USA/9.6.1990; EP346750B1 Europe/9.6.1993)

113. H.J. Mattausch, F. Matthiesen, M. Schoebinger, "Anordnung zur DPCM-Codierung von Fernsehsignalen", Priority: 14.6.88, Granted (JP02033287A2 Japan/2.2.1990; US4891698 USA/2.6.1990; EP346751B1 Europe/25.8.1993)

114. H.J. Mattausch, B. Hoppe, G. Neuendorf, D. Schmitt-Landsiedel, H.J. Pfleiderer and M. Wurm, "Statischer Speicher", Priority: 21.4.89, Granted (JP02294994A2 Japan/5.12.1990; US5170375 USA/8.12.1992; EP393434B1 Europe/3.1.1996)

115. H.J. Mattausch, B. Hoppe, G. Neuendorf, D. Schmitt-Landsiedel, H.J. Pfleiderer and M. Wurm, "Statische Speicherzelle", Priority: 21.4.89, Granted (JP02294992A2 Japan/5.12.1990; US5040146 USA/13.8.1991; EP393435B1 Europe/3.1.1996)

116. H.J. Mattausch, "Speicher-Architektur mit N unabhaengig adressierbaren Schreib-/Lese-Ports, die mit Speicherzellen mit nur einem Schreib-/Lese-Port auskommt", Priority: 16.9.97, Granted: (US6141287 USA/31.10.2000)

117. H.J. Mattausch, "Schaltung zur Behandlung eines Zugriffskonflikts in Multiportspeichern mit N unabhaengig addressierbaren Schreib-/Lese-Ports" Priority: 16.9.97, Granted: (JP11143763A2 Japan/28.5.1999)

filed

118. C. Hierold, H.J. Mattausch, "Bipolartransistor mit isoliertem Gate (IBGT) und monolithisch intergriertem Stromspiegel", Priority: 8.9.92

119. H. Brunner, Y. Gerstenmaier, H.J. Mattausch, "Diode mit hoher Stromfestigkeit und weichem Abschaltverhalten", Priority: 27.9.95

120. R. Allinger, H. Braun, M. Kerber, H.J. Mattausch, "Verfahren zur Herstellung von integrierten kapazitiven Strukturen", Priority: 2.8.96

121. H.J. Mattausch, "Common Memory", Priority: 12.2.99 (Japanese Patent Application No. 11-033753)

122. H.J. Mattausch, "Address and Data Transmission Circuit", Priority: 25.3.99 (Japanese Patent Application No. 11-081288)

123. M. Miura-Mattausch, T. Ono, H.J. Mattausch, "Nonvolatile Memory using Deep Level Capture of Carriers at Corner Structure of Gate Oxide Film", Priority: 18.5.99 (Japanese Patent Application No. 11-136710)

124. M. Miura-Mattausch, M. Tanaka, H.J. Mattausch, "MOSFET Type Semiconductor Device with Highly Doped Barrier Region", Priority: 18.5.99 (Japanese Patent Application No. 11-136768)

125. H.J. Mattausch, K. Kishi, N. Omori, "Multiport Cache Memory", Priority: 11.8.2000 (Japanese Patent Application No. 2000-244524)

126. H.J. Mattausch, T. Gyohten, "Associative Memory", Priority: 20.1.2001 (Japanese Patent Application No. 2001-11760)

127. T. Hironaka, H.J. Mattausch, K. Hiramatsu, "Parallel Processor", Priority: 19.4.2002 (Japanese Patent Application No. 2002-117913)

128. T. Koide, H.J. Mattausch, T. Morimoto, Y. Harada, "Picture Segmentation Method, Picture Segmentation Equipment, Real-Time Picture-Processing Method, Real-Time Picture-Processing Equipment and Picture-Processing Integration Circuit", Priority: 27.5.2002 (Japanese Patent Application No. 2002-152491)

129. H.J. Mattausch, T. Koide, "Winner-Line-Up Amplifier with Self-Adapting Maximum-Gain Region", Priority: 31.5.2002 (Japanese Patent Application No. 2002-159436)

130. H.J. Mattausch, T. Koide, "Pattern-Recognition System, Associative-Memory Equipment Contained in this System and Pattern-Recognition-Processing Method", Priority: 6.6.2002 (Japanese Patent Application No. 2002-165769)