日時：平成15年1月21日（火）1３：３0‐1５：00, 1月28日（火）1３：３0‐1５：00
場所：ナノデバイス・システム研究センター 東棟5階会議室
講演者：Prof. Zhou Xingn（COE招聘教授）
School of Electrical & Electronic Engineering, Nanyang Technological University, Singapore

（１）1月21日（火）

講演題目: MOSFET Compact I-V Modeling for Deep-Submicron Technology Development

講演内容:
A unified compact Ids model for deep-submicron (DSM) MOSFETs is developed. The model includes all major short-channel effects and covers full range of gate length (without "binning") and biases for a given technology, which requires minimum measurement data for parameter extraction following a prioritized two-iteration sequence. The fitting parameters all have their physical meanings and are extracted from a given technology, which can be correlated to true process variables for predicting process fluctuations on electrical performance and for aiding new technology development. The demonstrated approach to DSM MOSFET compact modeling represents a first step towards bridging technology developers and circuit designers.

（２）1月28日（火）

講演題目:Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution

講演内容:
A single-engine mixed-mode multi-level circuit simulator, XSIM, is introduced. The unique dynamic circuit partitioning and mode switching are based on the subcircuit expansion approach, in which digital gates have a dual-representation at the logic and circuit levels. A dynamic-delay model is described for gate-level timing simulation, which includes the effects of nonlinear capacitive loading, input transition time, and multiple-input triggering, and demonstrates near circuit-level accuracy with gate-level speed. A block-level representation for analog circuit acceleration is proposed. The proposed methodology will prove to be very useful for mixed-signal circuit design in the deep-submicron technology era.