[1] T. Maeda, A. Iwata, LSI IP Design Award, Development Encouragement Award, "Development of Low Phase Noise CMOS VCO with Frequency Range" (2002).

[2] S. Hosokawa, STARC Symposium, Special Award for Presentation (2002).

[3] Y. Mitani, H. Uchida, T. Hironaka, and H.J. Mattausch, and T. Koide "SuperH Compatible Instruction Set Processor IP for System LSI Research and Education," The 4th LSI IP Design Award, Challenge Award, LSI IP Design Award Committee, 2002.5. URL http://ne.nikkeibp.co.jp/award/

[4] T. Morimoto, Y. Harada, T. Koide, and H. J. Mattausch, "A real-time picture-segmentation architecture for intelligent information processing, "The 4th LSI IP Design Award, Development Encouragement Award, LSI IP Design Award Committee, 2002.5. URL http://ne.nikkeibp.co.jp/award/

[5] K. Johguchi, Z. Zhu, H. J. Mattausch, T. Koide, T. Hirakawa, and T. Hironaka, "Multi-Port Cache Design Based on Hierachcal Multi-Bank Memory Architecture", The 4th IEEE Hiroshima Student Symposium (HISS), Research Award, (2002).

[6] Y. Darma, 16th International Microprocesses and Nanotechnology Conference 2002 Award, young Author's Award (2002).

[7] T. Morie, M. Ishidu, H. Ando, A. Iwata, IP Award"Coarse Image Region Segmentation Using Resistive-fuse Networks" (2003).

[8] A. Iwata, Fellow of the Institute of Electronics, Information and Communication Engineers (2003).

[9] T. Koide, H.J. Mattausch, Y. Yano, T. Gyohten and Y. Soda, "A Nearest-Hamming-Distance Search Memory with Fully Parallel Mixed Digital-Analog Match Circuitry," The Asia and South Pacific Design Automation Conference (ASP-DAC2003), Special Feature Award, University Design Contest.

[10] S. Fukae, N. Ohmori, H. J. Mattausch, T. Koide, T. Inoue, and T. Hironaka, "Minimization of Transistor Numbers and Global Wiring Numbers by Distributed Crossbar Function for Realizing Bank-based Multiport Memories", The Institute of Electrical Engineers of Japan, Conference Paper and Presentation Award of the 54th Annual Technical Conference of the Chugoku Chapter of the Electronics and Information Institute (2003).

[11] K. Johguchi, Z. Zhu, H. J. Mattausch, T. Koide, T. Hirakawa, and T. Hironaka, "Combined Data/Instruction Multi-Port Cache Design Based on Hierachcal Multi-Bank Memory Architecture", The 5th IEEE Hiroshima Student Symposium (HISS), Research Award, (2003).

[12] T. Morimoto, "Research for Real-Time Image Segmentation Architecture and its Digital-CMOS Implementation," Hiroshima University Student Award, President of Hiroshima University, Taizou Muta, No. 1-0061, 2003.3.

[13] Navarro Dondee (Prof. Miuraﾕs Group), Special Award for Presentation, SRARC Symposium 2003, Poster Session, (2003.9.11).

[14] H. Sunami, Fellow of the Institute of Electronics, Information and Communication Engineers (2003).

[15] Y. Darma (Prof. Miyazakiﾕs Group), Solid State Devices and Materials, Young Researcher Award (2003).

[16] S. Miyazaki, Japanese Journal of Applied Physics Editorial Contribution Award (2003).

[17] Y. Yano, T. Koide, and H.J. Mattausch, "Fast, Compact, and Low-Power Minimum Hamming/Manhattan Distance Search Associative Memory Macro," The 6th LSI IP Design Award, IP Award, LSI IP Design Award Committee, 2004.5. URL http://ne.nikkeibp.co.jp/award/

[18] S. Miyazaki, Selete Award 2004, Achievement Award (2004).

[19] Y. Darma (Prof. Miyazakiﾕs Group), Hiroshima University, President's Distinction Award (2004).