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業績リスト：特許
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| I.回路システムアーキテクチャ |
II.デバイスモデリング |
III.ナノデバイスシステム |
[1] H.J. Mattausch and T. Koide, "Pattern matching and pattern recognition system, associative memory apparatus, and pattern matching pattern recognition processing method," JPN Patent Application No.2002-165759 (2002.05.31).
[2] H.J. Mattausch and T. Koide, "Self-adjusting winner lineup amplifier," JPN Patent Application No.2002-159436 (2002.06.06).
[3] T. Koide, H.-J. Mattausch, T. Morimoto, and Y. Harada, "Image segmentation method, image segmentation apparatus, image processing method, and image processing apparatus," JPN Patent Application No. 2002-152491, (2002.05.27).
[4] T. Hironaka，H.-J. Mattausch and T. Koide，T. Hirakawa, K. Johguchi, "Multi-port integrated cache," Japanese Patent Application 2002-320037 (2002.11.11).
[5] H.J. Mattausch and T. Koide, "Pattern matching and pattern recognition system, associative memory apparatus, and pattern matching pattern recognition processing method," USA Patent Application No.10/453,636 (2003.05.27).
[6] H.J. Mattausch and T. Koide, "Pattern matching and pattern recognition system, associative memory apparatus, and pattern matching pattern recognition processing method," EPC Patent Application No.03012722.9 (2003.05.27).
[7] H.J. Mattausch and T. Koide, "Pattern matching and pattern recognition system, associative memory apparatus, and pattern matching pattern recognition processing method," KOR Patent Application No.2003-36263 (2003.05.27).
[8] H.J. Mattausch and T. Koide, "Pattern matching and pattern recognition system, associative memory apparatus, and pattern matching pattern recognition processing method," TWN Patent Application No.92115261 (2003.05.27).
[9] H.J. Mattausch and T. Koide, "Self-adjusting winner lineup amplifier," USA Patent Application No.10/445,033 (2003.06.04).
[10] H.J. Mattausch and T. Koide, "Self-adjusting winner lineup amplifier," EPC Patent Application No.03011724.6 (2003.06.04).
[11] H.J. Mattausch and T. Koide, "Self-adjusting winner lineup amplifier," KOR Patent Application No.2003-34611 (2003.06.05).
[12] H.J. Mattausch and T. Koide, "Self-adjusting winner lineup amplifier," TWN Patent Application No.92114262 (2003.06.05).
[13] H. J. Mattausch, T. Koide, T. Hironaka, H. Uchida, K. Johguchi, Z. Zhu, " Memory with Synchronous Bank Architecture," Japanese Patent Application 2003-167989 (2003.6.12).
[14] H.J. Mattausch, T. Koide, M. Mizokami, "Recognition and Learning Method of Reference Data and Pattern-Recognition System," Japanese Patent Application 2003-434596 (2003.12.26).
[15] T. Koide, H.-J. Mattausch, T. Morimoto, and Y. Harada, "Image segmentation method, image segmentation apparatus, image processing method, and image processing apparatus," USA Patent Application No.10/445,247, (2003.05.26).
[16] T. Koide, H.-J. Mattausch, T. Morimoto, and Y. Harada, "Image segmentation method, image segmentation apparatus, image processing method, and image processing apparatus," EPC Patent Application No.03011840.0, (2003.05.26).
[17] T. Koide, H.-J. Mattausch, T. Morimoto, and Y. Harada, "Image segmentation method, image segmentation apparatus, image processing method, and image processing apparatus," KOR Patent Application No.2003-33324, (2003.05.26).
[18] T. Koide, H.-J. Mattausch, T. Morimoto, and Y. Harada, "Image segmentation method, image segmentation apparatus, image processing method, and image processing apparatus," TWN Patent Application No.92114142, (2003.05.26).
[19] T. Koide, H.-J. Mattausch, T. Morimoto, and Y. Harada, "Image segmentation apparatus, image segmentation method, and image segmentation integrated circuit," JPN Patent Application No. 2003-322163, (2003.09.12).
[20] T. Hironaka，H.-J. Mattausch and T. Koide，T. Hirakawa, K. Johguchi, "Multi-port integrated cache," USA Patent Application TBD (2003.10.06).
[21] H.J. Mattausch and T. Koide, "Associative Memory Apparatus for searching data in which Manhattan Distance is Minimum," JPN Patent Application No. 2004-017429 (2004.01.26).
[22] H.J. Mattausch, T. Koide, Y. Shirakawa, "Method for Reference-Data Optimization and Pattern-Recognition System," Japanese Patent Application 2004-053433 (2004.2.27).
[23] H. J. Mattausch, T. Koide, T. Hironaka, H. Uchida, K. Johguchi, Z. Zhu, "Memory with Synchronous Bank Architecture," No.TBD, (2004.2).
[24] H.J. Mattausch and T. Koide, "Associative Memory Apparatus for searching data in which Manhattan Distance is Minimum," USA, Patent Application No.TBD (2004.05.31).
[25] H.J. Mattausch and T. Koide, "Associative Memory Apparatus for searching data in which Manhattan Distance is Minimum," EPC Patent Application No.TBD (2004.05.31).
[26] H.J. Mattausch and T. Koide, "Associative Memory Apparatus for searching data in which Manhattan Distance is Minimum," KOR Patent Application No.TBD (2004.05.31).
[27] H.J. Mattausch and T. Koide, "Associative Memory Apparatus for searching data in which Manhattan Distance is Minimum", TWN Patent Application No.TBD (2004.05.31).
[28] H. J. Mattausch, T. Koide and M. Mizokami, "Reference Data Recognition and Learning Method and Pattern Recognition System," USA Patent Application No. TBD. (2004. 6. 15).
[29] H. J. Mattausch, T. Koide and M. Mizokami, "Reference Data Recognition and Learning Method and Pattern Recognition System," EPC Patent Application No. TBD. (2004. 6. 15).
[30] H. J. Mattausch, T. Koide and M. Mizokami, "Reference Data Recognition and Learning Method and Pattern Recognition System," KOR Patent Application No. TBD. (2004. 6. 15).
[31] H. J. Mattausch, T. Koide and M. Mizokami, "Reference Data Recognition and Learning Method and Pattern Recognition System," TWN Patent Application No. TBD. (2004. 6. 15).
[32] T. Koide, H.-J. Mattausch, T. Morimoto, and Y. Harada, "Image segmentation apparatus, image segmentation method, and image segmentation integrated circuit," USA Patent Application No. TBD, (2004.05.31).
[33] T. Koide, H.-J. Mattausch, T. Morimoto, and Y. Harada, "Image segmentation apparatus, image segmentation method, and image segmentation integrated circuit," EPC Patent Application No. TBD, (2004.05.31).
[34] T. Koide, H.-J. Mattausch, T. Morimoto, and Y. Harada, "Image segmentation apparatus, image segmentation method, and image segmentation integrated circuit," KOR Patent Application No. TBD, (2004.05.31).
[35] T. Koide, H.-J. Mattausch, T. Morimoto, and Y. Harada, "Image segmentation apparatus, image segmentation method, and image segmentation integrated circuit," TWN Patent Application No. TBD, (2004.05.31).
[36] 佐々木 守、岩田 穆、有薗 大介、特許出願人：岩田 穆
特願2004-10053：名称「半導体装置」、2004年1月19日出願.
[37] 亀田 成司、岩田 穆、佐々木 守、吉川 公麿、特許出願人：岩田 穆
出願番号H02-022317：名称「画像処理装置に関する特許」、2004年1月28日出願.
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| I.回路システムアーキテクチャ |
II.デバイスモデリング |
III.ナノデバイスシステム |
[38] 三浦道子、北丸大輔、"ポケット注入MOSFET敷居値電圧の計算方法"（特開平15-077934）, 公開日(2003.3.14).
[39] 三浦道子、中山範明、"半導体装置設計用シミュレーションモデル、半導体装置設計用シミュレーション装置、半導体装置設計用シミュレーション方法、ならびに半導体装置およびその製造方法"（特願2003-318947）, 出願日2003.9.10.
[40] 三浦道子、上野弘明、細川智士、 "半導体装置の設計用シミュレーションモデル、ドレイン電流熱雑音の解析方法、シミュレーション方法及びシミュレーション装置"（特願2003-420845）, 出願日2003.12.18.
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| TOP |
| I.回路システムアーキテクチャ |
II.デバイスモデリング |
III.ナノデバイスシステム |
[41] 半導体製造方法及装置(負イオンによるウェハ酸化防止方法)、藤井敏明、横山新、中華民国特願091109971,(2002.05.14).
[42] 半導体装置およびその製造方法、出願番号：2002-158788 (2002.05.31)出願人：科学技術振興事業団、発明者：中島安理.
[43] 半導体装置およびその製造方法、出願番号：2002-268342 (2002.09.13)出願人：株式会社半導体理工学研究センター、発明者：中島安理.
[44] Method of fabricating semiconductor device、出願番号：PCT/JP02/05386 (2002.05.31)、出願国：日本以外全指定、国際公開番号：WO 02/099868 (2002.12.12)、出願人（米国除く全ての指定国について）：東京エレクトロン、（米国についてのみ）：横山新、中島安理、多田吉秀、中村源志、今井正幸、米川司、発明者：横山新、中島安理、多田吉秀、中村源志、今井正幸、米川司.
[45] 半導体装置 特願2003-117826 2003.4.23出願人：科学技術振興事業団 発明者：吉川公麿、岩田穆、角南英夫、マタウシュ ハンスユルゲン、横山新、芝原健太郎、中島安理、小出哲士、エービーエム ハルン ウル ラシッド、渡邊慎司、「ＵＷＢ送受信可能なアンテナによる半導体基板上および基板間の通信機能を有する半導体装置」.
[46] 屈折率膜の積層方法およびパターン化積層体、出願番号：2003-081181 (H15.03.24)、出願人：広島大学長、発明者：中島安理、横山新、吉川公麿、和気勝.
[47] Semiconductor device and method for manufacturing same、出願番号：10/437119 (2003.05.14) 、出願国：米国、出願人：株式会社半導体理工学研究センター、 発明者：中島安理.
[48] 半導体ウェハ及びこれを用いた半導体装置の製造方法（発光素子の集積化方法）、荻原光彦、藤原博之、横山新、特願MA901355,(2003.09.29).
[49] 芝原健太郎、"ＭＯＳ型半導体装置及びその製造方法"(特願2003-311387)、2003.9.3.
[50] 村川正宏、芝原健太郎、小田嘉則、樋口哲也、西謙二、"特性値の推定方法、その推定方法の実施に使用する装置および、その推定の実施のための処理プログラム"(特願2003-320495)、(2003.9.12).
[51] 有機レーザーおよびその製造方法、特願2004-099015 (2004.03.30)、出願人：財団法人ひろしま産業振興機構 発明者：中島安理.
[52] 炭素を含む材料から成る突起を形成する方法、炭素を含む材料から成る突起を有する基板生産物、および電子放出素子、西林良、宮崎富仁、今井貴浩、田部井哲夫、横山新、特願2004-123383.
[53] 突起構造の形成方法、突起構造、および電子放出素子、西林良、宮崎富仁、今井貴浩、田部井哲夫、横山新、特願2004-123379.
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